Format |
Syntax: |
Operation: |
Operands: |
Architecture revision |
Opcode | ||||||||||||
1 |
paddh.ub Rd, Rx, Ry |
Rd[31:24] = LSR(ZE(Rx[31:24], 9) + ZE(Ry[31:24], 9), 1) ; Rd[23:16] = LSR(ZE(Rx[23:16], 9) + ZE(Ry[23:16], 9), 1); Rd[15:8] = LSR(ZE(Rx[15:8], 9) + ZE(Ry[15:8], 9), 1); Rd[7:0] = LSR(ZE(Rx[7:0], 9) + ZE(Ry[7:0], 9), 1); |
{d, x, y} ∈ {0, 1, …, 15} |
Rev1+ |
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2 |
paddh.sh Rd, Rx, Ry |
Rd[31:16] = ASR(SE(Rx[31:16], 17) + SE(Ry[31:16], 17), 1); Rd[15:0] = ASR(SE(Rx[15:0], 17) + SE(Ry[15:0], 17), 1); |
{d, x, y} ∈ {0, 1, …, 15} |
Rev1+ |
|
Perform addition of four pairs of packed unsigned bytes (paddh.ub) or two pairs of packed signed halfwords (paddh.sh) with a halving of the result to prevent any overflows from occuring.
Q: |
Not affected. |
V: |
Not affected. |
N: |
Not affected. |
Z: |
Not affected. |
C: |
Not affected. |